Skip to main content
Log in

An area and power optimization technique for CMOS bandgap voltage references

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in the technology and also the area of bipolar transistors. The proposed technique does not depend on a special process and can be applied for designing bandgap reference circuits with different topologies.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

References

  1. Kujik, K. E. (1973). A precision reference voltage source. IEEE Journal of Solid-State Circuits, 8(3), 222–226.

    Article  Google Scholar 

  2. Tsividis, Y. P., & Ulmer, R. W. (1978). A CMOS voltage reference. IEEE Journal of Solid-State Circuits, 13(6), 774–778.

    Article  Google Scholar 

  3. Tzanateas, G., Salama, C. A. T., & Tsividis, Y. P. (1979). A CMOS bandgap reference. IEEE Journal of Solid-State Circuits, 14(3), 655–657.

    Article  Google Scholar 

  4. Song, B., & Gray, P. R. (1983). A precision curvature-compensated CMOS bandgap reference. IEEE Journal of Solid-State Circuits, 18(6), 634–643.

    Article  Google Scholar 

  5. Brooks, T., & Westwisk, A. L. (1994). A low-power differential CMOS bandgap reference. In ISSCC Dig. of Tech. Papers (pp. 248–249).

  6. Tham, K., & Nagaraj, K. (1995). A low supply voltage high PSRR voltage reference in CMOS process. IEEE Journal of Solid-State Circuits, 30(5), 586–590.

    Article  Google Scholar 

  7. Buck, A. E., et al. (2002). A CMOS bandgap reference without resistors. IEEE Journal of Solid-State Circuits, 37, 81–85.

    Article  Google Scholar 

  8. Tsividis, Y. P. (1980). Accurate analysis of temperature effects in IC-VBE characteristics with application to bandgap reference sources. IEEE Journal of Solid-State Circuits, 15, 1076–1084.

    Article  Google Scholar 

  9. Lin, S. L., & Salama, C. A. T. (1985). A Vbe (T) model with application to bandgap reference design. IEEE Journal of Solid-State Circuits, 20(6), 1283–1285.

    Article  Google Scholar 

  10. van Staveren, A., et al. (1996). The design of low-noise bandgap references. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 43(4), 290–300.

    Article  Google Scholar 

  11. HSPICE Users Manual-Elements and Device Models, Meta-Software Inc. (1996).

  12. Varzaghani, A. (2000). Bandgap voltage reference design. Technical Report, Emad Semicon.

  13. Mehrmanesh, S., Vahidfar, M. B., Aslanzadeh, H. A., & Atarodi, M. (2003). A 1-volt, high PSRR, CMOS bandgap voltage reference. In Proceedings of International Circuits and Systems (ISCAS) (Vol. I, pp. 381–384).

  14. Cabrini, A., De Sandre, G., Gobbi, L., Malcovati, P., Pasotti, M., Poles, M., Rigoni, F., & Torelli, G. (2005). A 1 V, 26 μW extended temperature range band-gap reference in 130-nm CMOS technology. In Proceedings of European Solid-State Circuit Conference (ESSCIRC) (pp. 503–506), Grenoble.

  15. Leung, K. N., & Moke, P. K. T. (2002). A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device. IEEE Journal of Solid-state Circuit, 37(4), 526–529.

    Article  Google Scholar 

  16. Tajalli, A., Atarodi, M., Khodaverdi, A., & Sahandi Esfanjani, F. (2004). Design and optimization of a high PSRR CMOS bandgap voltage reference. In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) (Vol. I, pp. 45–48).

Download references

Acknowledgments

This work has been partially supported by Emad Semicon. The authors would like to appreciate A. Daneshfar from Emad Semicon and M. Nasrollahi from MERDCI for their valuable help in this work.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Armin Tajalli.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Tajalli, A., Chahardori, M. & Khodaverdi, A. An area and power optimization technique for CMOS bandgap voltage references. Analog Integr Circ Sig Process 62, 131–140 (2010). https://doi.org/10.1007/s10470-009-9344-4

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-009-9344-4

Keywords

Navigation